High-Performance Mitsubishi CPU Unit A3NCPU – Reliable & Durable PLC Processor
Mitsubishi CPU Unit A3NCPU
The Mitsubishi A3NCPU CPU unit features 2048 I/O points and 2048 I/O data device points, with a program capacity of 30k steps. The basic instruction execution speed (LD command) is 1.0μs. It uses a cyclic scan method consisting of input sampling, program execution, and output refresh. During the input refresh phase, when the input port is closed, new input states during program execution are not read until the next scan cycle. The content of the component image register changes as the program executes. The scan cycle length depends on CPU instruction speed, instruction execution time, and the number of instructions. Due to centralized sampling and output, there is an I/O response delay. User program storage capacity is measured in words or K words (1 word = 16 bits, 1K = 1024 words). Logic operation instructions typically occupy 1 word, timer/counter and shift instructions occupy 2 words, and data operation instructions occupy 2 to 4 words.
The Mitsubishi A3NCPU is a central processing unit designed for the A series programmable logic controllers (PLCs). It supports a maximum of 2048 input/output points and an equal number of input/output data device points, providing substantial capacity for medium to large-scale industrial automation applications. The program memory capacity is 30k steps, which allows for the storage of complex control logic sequences.
The basic instruction execution speed, specifically for the LD (Load) command, is 1.0 microseconds, indicating a relatively fast processing capability for its generation. The A3NCPU employs a fixed cyclic scan method, which includes three distinct phases: input sampling, program execution, and output refresh. During the input sampling phase, all input signals are read simultaneously and stored in the input image register. The program execution phase then processes the stored data, and finally, the output refresh phase updates all output terminals simultaneously based on the output image register.
A notable characteristic of this scan cycle is that when the input port is closed during the input refresh process, any new input states that occur during program execution cannot be read. These new states are only accepted during the next scan cycle, which contributes to the inherent input/output response delay. The content of the component image register changes dynamically as the program executes, reflecting the current logic state.
The total scan cycle time is determined by three factors: the execution speed of the CPU, the time required for each instruction, and the total number of instructions in the user program. Because the system uses centralized sampling and centralized output, there is a noticeable input/output lag, meaning that the response to external events is delayed by at least one scan cycle.
User program storage capacity is a key specification for measuring how much application logic can be stored. It is typically expressed in words or K-words, where one word equals 16 binary bits, and 1024 words equal 1K word. The PLC stores instructions and data in units of words. For example, basic logic operation instructions generally occupy one word each, while timer/counter and shift instructions occupy two words, and data operation instructions may occupy two to four words depending on their complexity.
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